Forbidden pitches in Sub-Wavelength Lithography and their Implications on Design

Moore’s Law has been the most important benchmark for microelectronics development over the past four decades. It has been interpreted to mean that critical dimensions (CD) of a design must shrink geometrically over time. The chip-level integration of devices has been possible through concurrent improvement in lithographic resolution. The lithographic resolution was primarily improved by moving deeper into ultraviolet spectrum of light. However, the wavelength of the optical source used for lithography has not improved for nearly a decade. This has lead to the development of sub-wavelength lithography. The diffraction effects of sub-wavelength lithography were offset by optical proximity correction (OPC), phase shift masking (PSM) and impending move to immersion lithography. Unfortunately, one time benefits from each of these resolution enhancement techniques (RET) have nearly exhausted. In this paper, we explore one important diffraction aspect of sub-wavelength lithography viz. the forbidden pitch phenomenon and its implication on future designs. We studied Forbidden pitches in context of 65nm and 45nm technologies using aerial imaging simulation. Aerial imaging simulation is computationally expensive and is not possible to perform on entire layout structures. Based on results from our simulations on selected patterns, we observe that in absence of any other resolution enhancement technique, many of the current layout patterns will be disallowed in 45nm technology. Such restrictions significantly mitigate the benefit of migration to 45nm technology in terms of area, power and performance of a design. We further show that even structured gate array based designs are not immune to this problem.